TWILIGHT aims to address the transformation of next generation datacenters by bringing InP membranes and InP-HBT electronics at unprecedently close distances (<20um) to unleash the speed capabilities of its high performance components and to enable 112Gbaud per lane.
Wafer-scale bonding together with high-accuracy assembly and co-packaging concepts, TWILIGHT's optoelectronic engines will be capable of up to 1.6T capacity. Selective area growth will be exploited to develop C-band and O-band EMLs and UTC photodiodes in combination with echelle gratings on the same system-on-chip platform. Adaptation of the SAG layerstack will be used to develop polarization insensitive SOAs enabling complex functionalities on chip.
TWILIGHT will leverage analog bandwidth interleaving for interfacing its transceivers with next generation 112G SERDES and will develop analog (de)multiplexers, >110GHz linear drivers and 100GHz TIAs. TWILIGHT will exploit the PI-SOAs to develop 4×4 and16x16 optical space switches exhibiting nanosecond latency and >50% smaller footprint. The O-band and Cband SiP transceiver demonstrators leverage up to 72% and 74% power consumption savings compared to established technologies and target the datacentre market (2-10km) and DCI (<40km), respectively, with estimated cost 0.89€/Gb/s.